1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof and, more particularly to a semiconductor device having a conductive layer including copper and a manufacturing method thereof.
2. Description of the Background Art
With recent increase in demand for higher integration degree and speed of the semiconductor device, various considerations are given to the material of a conductive layer. If a width of the conductive layer becomes smaller than about 0.15 xcexcm, the selection of materials which can be used for the conductive layer would extremely be limited. Recently, the use of copper for the conductive layer has been described for example in xe2x80x9cDamascene Cu interconnection capped by TiWN layerxe2x80x9dTECHNICAL REPORT OF IEICE, SDM 96-169 (1996-12).
FIG. 29 is a cross sectional view showing a structure of the conductive layer which is described in the aforementioned article. Referring to FIG. 29, a trench 92 is formed in an insulating layer 91 including silicon dioxide and formed on a silicon substrate. A conductive layer 94 including copper is formed in trench 92 with a barrier layer 93 including titanium nitride, tantalum or tantalum nitride in the interposed. A cap layer 96 including titanium tungsten nitride (TiWN) is formed to cover an upper surface of conductive layer 94. Barrier layer 93 and cap layer 96 effectively prevent oxidation of conductive layer 94 and diffusion of copper in conductive layer 94 into insulating layer 91, so that degradation of characteristic such as increase in electrical resistance of conductive layer 94 is effectively prevented.
Conventionally, a so-called dual damascene structure as shown in FIG. 29 in which a multiple of conductive layers including copper are formed is described, for example, in 1997 Symposium on VLSI Technology Digest of Technical Papers pp. 59-60. FIGS. 30 to 38 are cross sectional views showing a method of manufacturing the dual damascene structure described in the above mentioned document. Referring to FIG. 30, an insulating layer 101 including silicon dioxide is formed on a silicon substrate, and a trench 102 is formed in insulating layer 101. A first layer including titanium nitride, tantalum or tantalum nitride is formed to cover a surface of trench 102, and a copper layer is formed on the first layer to fill trench 102. The copper and first layers are planarized by CMP (Chemical Mechanical Polishing), so that a barrier layer 103 including titanium nitride, tantalum or tantalum nitride and a conductive layer 104 including copper are formed.
Formed on insulating layer 101 are a barrier layer 105 including silicon nitride, an insulating layer 106 including silicon dioxide, a barrier layer 107 including silicon nitride, an insulating layer 108 including silicon dioxide and a barrier layer 109 including titanium nitride, tantalum or tantalum nitride. By sequentially etching these layers, holes 111 and 110 are formed.
As shown in FIG. 31, when the etching is finished, a particle 112 of carbon fluoride (CFx), a particle 113 of cupric oxide (CuO), a particle 116 of copper fluoride (CuFx) or the like adhere to a sidewall of hole 110. A cupric oxide layer 114 is formed on a surface of conductive layer 104, and a cuprous oxide (Cu2O) layer 115 is formed therebelow. It is noted that barrier layers 103, 105, 107 and 109 as well as insulating layer 108 are not shown in FIGS. 31 to 34.
Referring to FIG. 32, oxygen plasma allows particles 112 and 116 of carbon and copper fluoride to be oxidized and disappeared.
Referring to FIG. 33, an oxide is reduced by hydrofluoric acid (HF). Thus, particle 113 of cupric oxide disappears and, cupric oxide layer 114 in conductive layer 104 is also reduced to form cuprous oxide layer 115.
Referring to FIG. 34, cuprous oxide layer 115 is reduced by gaseous hydrogen to copper.
Referring to FIG. 35, a barrier layer 121 including titanium nitride, tantalum or tantalum nitride is formed to cover side surfaces of holes 110 and 111 and the surface of conductive layer 104.
Referring to FIG. 36, an entire surface of barrier layer 121 is etched back to expose the surface of conductive layer 104.
Referring to FIG. 37, a copper layer 123 is formed by CVD (Chemical Vapor Deposition).
Referring to FIG. 38, an entire surface of the copper layer is etched back by CMP to form a conductive layer 124 including copper. Thus, a dual damascene structure in which conductive layers 104 and 124 are connected is completed.
In the above described method, however, a step of cleaning hole 110 as shown in conjunction with FIGS. 32 to 34 is required after holes 110 and 111 are formed, whereby the number of steps for manufacturing the semiconductor device disadvantageously increases.
Further, if hole 110 is formed with a diameter larger than a width of trench 102 in the step shown in FIG. 30 such that a width of conductive layer 124 filling hole 110 is increased, a surface of insulating layer 101 is exposed by hole 110. If hole 110 is filled with copper layer 123, the copper is oxidized as it is in contact with silicon dioxide, so that electrical resistance of conductive layer 124 increases. In addition, as copper is diffused into insulating layer 101, insulating characteristic of insulating layer 101 is impaired.
The present invention is made to solve the aforementioned problem. An object of the present invention is to provide a semiconductor device having a conductive layer capable of effectively preventing diffusion of particles of copper or the like which form the conductive layer without any increase in the number of manufacturing steps.
Another object of the present invention is to provide a semiconductor device in which particles of copper or the like forming a conductive layer are not diffused to an insulating layer even when a width of the conductive layer is increased.
A semiconductor device according to the present invention includes a first insulating layer, first diffusion preventing layer, first conductive layer, second diffusion preventing layer, second insulating layer, third diffusion preventing layer and second conductive layer.
The first insulating layer is formed on a semiconductor substrate and has a recess. The first diffusion preventing layer is formed on a surface of the recess. The first conductive layer is formed on a surface of the first diffusion preventing layer to fill the recess. The second diffusion preventing layer is formed on a surface of the first insulating layer and provided with an opening which exposes a surface of the first conductive layer. The second insulating layer is formed on a surface of the second diffusion preventing layer to expose the surface of the first conductive layer and a part of the surface of the second diffusion preventing layer, and has a first hole communicating with the opening. The third diffusion preventing layer is formed on a side surface of the first hole and on the second insulating layer in contact with an upper surface of the second diffusion preventing layer. The second conductive layer fills the opening and the first hole such that it is in contact with the first conductive layer.
In the semiconductor device having the above described structure, a side surface of the opening is formed by the part of the surface of the second diffusion preventing layer, the side surface of the first hole is formed by the third diffusion preventing layer, and the third diffusion preventing layer is in contact with the upper surface of the second diffusion preventing layer. Thus, the portion of the second conductive layer which fills the opening and the first hole is in contact with the second and third diffusion preventing layers, so that the second conductive layer would not be in contact with the insulating layer even if a diameter of the first hole and a width of the first conductive layer are increased. As a result, atoms of the second conductive layer would not be diffused into the insulating layer. In addition, increase in electrical resistance of the second conductive layer is prevented.
Preferably, the diameter of the first hole is larger than that of the opening.
Further, the third diffusion preventing layer preferably includes fourth and fifth diffusion preventing layers which are respectively formed on the side surface of the first hole and on the second insulating layer.
Preferably, the semiconductor device further includes a fourth diffusion preventing layer formed on a portion of the third diffusion preventing layer which is formed on the side surface of the first hole. In this case, as two diffusion preventing layers are formed on the side surface of the first hole, the diffusion of atoms forming the second conductive layer is more effectively be prevented.
More preferably, the semiconductor device further includes a third insulating layer formed on the second insulating layer, where the third insulating layer has a second hole communicating with the first hole and the third diffusion preventing layer is formed on the side surfaces of the first and second holes and on the third insulating layer. In this case, if the second hole is filled with a conductive layer, another conductive layer can be formed.
Preferably, the first and second conductive layers include copper, and the first and second insulating layers include silicon dioxide.
Preferably, the first and third diffusion preventing layers include at least one material selected from a group of titanium nitride, tantalum or tantalum nitride, and the second diffusion preventing layer includes silicon nitride. In this case, as the first and third diffusion preventing layers which are respectively in contact with the first and second conductive layers in a large area include at least one material selected from the group of titanium nitride, tantalum or tantalum nitride, which are all conductors. Thus, electrical resistance of the first and second conductive layers is not increased. Further, as the second diffusion preventing layer formed between the first and second insulating layers includes silicon nitride, which is an insulator, the problem associated with short-circuit is avoided even when the silicon nitride is brought into contact with another conductive layer.
A method of manufacturing a semiconductor device according to the present invention includes the steps of:
forming a first insulating layer having a recess on a semiconductor substrate;
forming a first diffusion preventing layer on a surface of the recess;
forming a first conductive layer on a surface of the first diffusion preventing layer to fill the recess;
forming a second diffusion preventing layer on surfaces of the first conductive and insulating layers;
forming a second insulating layer on a surface of the second diffusion preventing layer;
selectively removing the second insulating layer to form a first hole which exposes a portion of the second diffusion preventing layer;
forming a third diffusion preventing layer on a side surface of the first hole in contact with an upper surface of the second diffusion preventing layer;
removing the exposed portion of second diffusion preventing layer using the second insulating layer and the third diffusion preventing layer as masks to form an opening which communicates with the first hole and exposes a portion of the first conductive layer; and
filling the opening and the first hole to form a second conductive layer in contact with the first conductive layer.
In the method of manufacturing the semiconductor device having the above described steps, the third diffusion preventing layer is formed on the sidewall of the first hole when the exposed portion of the second diffusion preventing layer is removed. Thus, for removing the first diffusion preventing layer, even when a particle comes from the first conductive layer therebelow, contact between the particle and the second insulating layer is prevented by the third diffusion preventing layer. As a result, the semiconductor device is provided which has a connection structure capable of effectively preventing diffusion of the particle or the like forming the conductive layer without any step of cleaning the hole which has conventionally been used.
Preferably, the step of forming the third diffusion preventing layer includes forming a third diffusion preventing layer on a surface of the exposed portion of the second diffusion preventing layer, side surface of the first hole and the second insulating layer. The method of manufacturing the semiconductor further includes a step of removing a portion of the third diffusion preventing layer on the surface of the portion of the second diffusion preventing layer to expose the portion of the second diffusion preventing layer.
Preferably, the step of forming the first hole includes forming the first hole having a diameter which is larger than a width of the first conductive layer, and the step of forming the opening includes forming a resist pattern with a hole pattern having a diameter which is equal to or smaller than the width of the first conductive layer on the surface of the second diffusion preventing layer such that a portion of the second diffusion preventing layer on the first conductive layer is exposed and removing the exposed portion of the second diffusion preventing layer using the resist pattern as a mask. In this case, as the first hole having a large diameter is formed, electrical resistance of the second conductive layer which fills the first hole can be reduced. Further, as the portion of the second diffusion preventing layer is removed in accordance with the resist pattern with the hole pattern having a width which is equal to or smaller than the width of the first conductive layer, the diameter of the opening formed in the second diffusion preventing layer would be equal to or smaller than the diameter of the first conductive layer. Thus, the first insulating layer is not exposed and contact between the first and second insulating layers is prevented.
Preferably, the method further includes a step of forming a fourth diffusion preventing layer on a surface of the second insulating layer, and the step of forming the first hole includes forming the first hole by selectively removing the fourth diffusion preventing layer and the second insulating layer.
Preferably, the method further includes a step of forming the fourth diffusion preventing layer on surfaces of the portion of the first conductive layer, third diffusion preventing layer and second insulating layer which have been exposed by removing the second diffusion preventing layer, and the step of forming the second conductive layer includes filling the opening and the first hole to form the second conductive layer which is in contact with the fourth diffusion preventing layer.
In this case, two diffusion preventing layers, that is, the third and fourth diffusion preventing layers, are formed on a sidewall of the first hole.
Preferably, the method further includes a step of forming a third insulating layer on the surface of the second insulating layer and a step of selectively removing the third insulating layer to form a second hole in the third insulating layer. In such manufacturing method, another conductive layer can be formed in the second hole.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.